A passing electrical test cannot rule out a cracked ceramic capacitor. Learn how to trace MLCC flex cracks to depaneling and assembly steps, measure PCB strain, tell flex damage from electrical overstress, and decide when soft termination capacitors help.
A board can pass electrical testing and still contain the beginning of its next field failure. Depanelization, connector insertion, screw fastening, or enclosure assembly can load a multilayer ceramic capacitor mechanically after the test that supposedly proved the board was good. The engineering challenge is therefore not just to find a shorted capacitor, but to identify when an MLCC flex crack was introduced and prevent electrically quiet damage from leaving production. [1][6]
An MLCC is a ceramic structure containing multiple internal electrodes, connected to external terminations that are soldered to the PCB. Board deformation can transfer mechanical strain through those soldered connections into the brittle ceramic body. The resulting crack need not produce an immediate, detectable electrical failure. [2][6]
For failure analysis, separate three events:
Those events should not be assumed to occur together. A visible crack, an intermittent short, and a capacitance shift are different observations, and none alone establishes the initiating cause. The supplied placement-review guidance explicitly cautions against attributing every damaged capacitor to board flex without examining the evidence. [1]
Two production scenarios deserve different responses. In the first, the board passes in-circuit test and is subsequently damaged during separation or assembly. That is a test-sequence coverage gap. In the second, damage already exists during testing but does not produce a failure under the applied test conditions. That is a latent-defect detection problem.
Moving the final electrical test later helps with the first scenario. It does not, by itself, solve the second.
The useful question is not simply, “How far is this capacitor from the edge?” It is, “What loads reach this location, through which supports, during every operation the product experiences?”
The research identifies depanelization, connector insertion, enclosure assembly, handling, press-fit operations, screw tightening, rework, and mechanical or thermal shock as relevant damage sources. It also emphasizes that local deformation and component orientation matter, not merely distance from a separation line. [1][6]
Overlay the assembly drawing with:
Then add the actual operation sequence. A board supported beneath a connector during test may be supported only at its corners when that connector is mated during final assembly. A capacitor away from the perimeter can still lie directly between an applied force and a distant support. [1]
Observe the work rather than relying exclusively on instructions. Ask operators to demonstrate how they remove boards from fixtures, separate panels, insert cables, and fit assemblies into housings. The largest deformation may occur during an unrecorded transition between nominally controlled steps. [1]
Capacitor orientation should be evaluated relative to the actual deformation direction. Manufacturer guidance summarized in the research supports reviewing both mounting orientation and position relative to board breaks. [1]
As a layout hypothesis, consider whether the deformation tends to separate the capacitor’s two soldered ends. Where practical, evaluate an orientation that reduces that loading. Confirm the benefit with measurement or supplier-supported analysis rather than applying a universal instruction to rotate every capacitor near an edge.
Likewise, moving a part inward is not automatically sufficient. A nearby slot or mounting feature may concentrate deformation at the new location. Treat the board as a loaded mechanical structure, not a collection of independent edge-clearance rules. [1]
A shorted MLCC identifies the failed element, not necessarily the original failure mechanism. The investigation should preserve competing hypotheses until operation history, electrical evidence, and physical analysis agree.
The following table is a diagnostic planning aid. Its observations are clues to investigate, not stand-alone proof.
| Investigation question | Evidence that strengthens a flex-damage hypothesis | Evidence that strengthens an electrical-overstress hypothesis | Important limitation |
|---|---|---|---|
| When did the failure first appear? | After depanelization, fastening, connector insertion, or handling | After startup, a switching event, or an abnormal supply condition | Detection time may differ from damage time |
| Where do failures cluster? | Near a shared load path, support gap, tab, connector, or screw | On nodes exposed to a common voltage waveform | Mechanical and electrical risks can coexist |
| What changes the failure rate? | A controlled support or assembly-process change | A verified reduction in electrical stress | Change one variable at a time where practical |
| What does physical analysis show? | A fracture path consistent with the proposed mechanical loading | Damage consistent with electrical breakdown and the measured waveform | Secondary damage can obscure the initiating event |
| What happened to comparable parts? | Mechanically exposed locations are affected more often | Electrically stressed nodes are affected more often | Use matched samples and preserve lot information |
The basis for this approach is evidence correlation: retain suspect boards, record the operation after which the issue appeared, compare locations and lots, and obtain strain measurement or component analysis where needed. [1]
Do not repeatedly bend a suspect assembly to demonstrate an intermittent short. That can extend damage and make the original condition harder to interpret. Similarly, repeated unrestricted power application can alter the failed component before a laboratory examines it.
A practical evidence-preservation procedure is to:
These are investigation controls, not a claim that a particular reading proves flex damage. The aim is to preserve enough evidence to test alternative explanations.
For an overstress investigation, compare the selected part’s rating and operating requirements with the voltage actually appearing across its terminals. Include relevant startup, shutdown, switching, and abnormal operating conditions in the measurement plan.
Do not infer margin from nominal rail voltage alone. The component-selection research emphasizes actual waveform capability, rated voltage, dielectric, termination construction, temperature, and the exact part number, not just capacitance and package. [2][4]
Also separate DC-bias capacitance reduction from physical damage. Class II MLCCs can lose effective capacitance under applied DC voltage, with the magnitude depending on the specific component. A low capacitance result under bias is therefore not automatically evidence of a cracked body. Compare measurements with the exact manufacturer’s bias data and test conditions. [2][4]
External appearance and electrical behavior answer different questions. Visual inspection can document accessible damage and assembly condition, but it cannot establish the integrity of every internal ceramic layer.
The research describes mechanical damage as potentially latent and difficult to screen in production. It also notes that a capacitor can pass electrical testing before a later operation damages it. Both limitations matter when interpreting a “no defect found” result. [1][5]
Build the inspection plan around what each method can establish:
| Method | Useful purpose | What a passing result does not establish |
|---|---|---|
| External visual inspection | Document exposed damage, placement, solder condition, and handling marks | That the internal ceramic is intact |
| AOI | Check visible assembly features within the system’s coverage | That every hidden fracture is absent |
| Capacitance measurement | Detect an electrical change under defined conditions | That all mechanically damaged parts have changed capacitance |
| Insulation-resistance or leakage testing | Evaluate isolation under the chosen voltage, time, and environment | That damage cannot manifest under different conditions |
| Laboratory imaging | Investigate internal features using a technique selected for the component | That an undetected crack is impossible |
| Controlled cross-sectioning | Examine a selected internal plane and fracture path | That the chosen plane intersects every defect |
For laboratory imaging, discuss feasibility and sensitivity with the analyst. Do not write “X-ray passed” into a disposition as if all imaging configurations provide equivalent crack detection. Likewise, destructive sectioning needs a plan: a negative result is meaningful only in relation to the planes examined and the suspected damage location.
Place functional and relevant isolation checks after the last significant mechanical assembly step where practical. If connectors are installed or screws tightened after final test, document that remaining exposure explicitly.
For process characterization, introduce temporary checkpoints before and after suspected operations. This helps narrow the interval in which electrical behavior changes. However, if all samples remain electrically acceptable while the process imposes excessive strain, the answer is not to declare the process safe. Electrical screening and mechanical-process validation must remain separate lines of evidence.
Strain measurement makes an invisible process variable observable. It does not directly detect a crack, and it does not provide a universal conversion from board strain to capacitor lifetime.
A useful audit captures the real operation, identifies local deformation near vulnerable components, and compares the result with an acceptance basis appropriate to the selected parts and product.
Specify what the audit must decide. Examples include:
State the board revision, thickness, stackup, panel configuration, component population, fixture revision, and assembly sequence. Without those identifiers, a passing audit can become detached from the process it actually evaluated.
Place gauges where they can meaningfully characterize the suspect load path. Include vulnerable capacitor locations and useful comparison locations, rather than measuring only a convenient open area.
The supplied instrumentation article discusses strong local strain gradients near components and mentions placement distances on the order of 1.5 mm. That should prompt careful location documentation, not become a universal gauge-spacing rule. A nearby reading is still a reading at the gauge grid, not necessarily the maximum strain at the capacitor attachment. [3]
Record gauge-grid centers, orientation, board side, and distance to the component on a mechanical drawing. If the capacitor occupies the ideal measurement position, discuss a representative instrumented assembly or another correlation method with the test specialist. Document any difference from the production configuration.
A three-element strain rosette commonly uses grids at 0°, 45°, and 90°. Simultaneous readings allow the in-plane strain state and principal strain directions to be calculated, rather than assuming that a single gauge aligns with the most important deformation. [3]
For readings εa, εb, and εc at those angles, the principal strains are:
ε1, ε2 = (εa + εc)/2
± sqrt[ ((εa - εc)/2)^2
+ (εb - (εa + εc)/2)^2 ]
Retain the raw channels as well as the derived values. A useful engineering comparison includes peak strain, its direction, the time history, and the operation that produced it. Recording only one maximum number discards information needed to distinguish a brief separation event from sustained enclosure distortion.
Depanelization can involve short-duration events. The instrumentation research describes simultaneous sampling at 50 kHz with a 10 kHz anti-aliasing filter as an acquisition configuration for such audits. These values are useful reference points, not universal requirements for every process. [3]
Have the measurement specialist select sampling, filtering, triggering, and recording duration based on the event bandwidth and the test objective. Verify that channel synchronization and filtering preserve the relationships needed for rosette calculations.
Calculate strain rate from the time history with a documented numerical method. Differentiation can amplify measurement noise, so the derivative method and any filtering should be part of the report rather than hidden software defaults.
Capture more than one carefully performed demonstration. The audit plan should cover meaningful process variation, such as different operators, panel locations, fixture loading conditions, and permitted assembly sequences.
Synchronize the strain record with an operation log or video. A peak is much easier to correct when it can be tied to a specific action: fixture release, connector insertion, tab separation, or enclosure closure.
Where feasible, measure both the original process and the proposed correction on otherwise comparable assemblies. The point is to establish causality, not merely collect an impressive waveform.
IPC/JEDEC-9704 is relevant to board strain measurement, but do not treat an online summary as a universal MLCC qualification rule. Verify the applicable document revision and obtain component-specific guidance from the capacitor supplier.
The supplied instrumentation source includes specific strain thresholds and assertions about standard-mandated actions. Those claims should not be copied into a production specification without checking the primary standard. In particular, do not assume that a limit discussed for another package or interconnect establishes the fracture threshold of the selected MLCC. [3]
The report should distinguish:
The strongest prevention strategy combines placement, tooling, controlled handling, and appropriate component construction. The research repeatedly warns that soft terminations do not make a mechanically poor layout safe. [1][4]
Start with the applied force and its nearest effective support. Adding appropriate support beneath a connector insertion area may address the mechanism more directly than moving every nearby capacitor. [1]
Review whether vulnerable MLCCs can be moved away from separation lines, tabs, mounting holes, press-fit locations, or narrow board sections. Evaluate orientation and pad geometry using the component supplier’s guidance. [1][6]
Keep the electrical consequences visible. Moving a decoupling capacitor can increase connection length and compromise the intended low-inductance current path. The supplied PCB guide explicitly frames MLCC layout as a balance between low electrical loop inductance and low mechanical strain. [6]
Sometimes the right answer is to change the fixture rather than the capacitor location. Sometimes it is to relocate bulk capacitance while retaining appropriate local decoupling. Validate both the mechanical and electrical outcome.
Specify the permitted separation method, support locations, and operation sequence. A generic instruction to “avoid bending” is not a reproducible process requirement.
Compare candidate depanelization methods on representative populated panels using the strain workflow above. Do not assume a named process is automatically safe independent of panel geometry, support, tool condition, and operator interaction.
Apply the same discipline to fastening and connector installation:
The research specifically recommends keeping placement changes tied to tooling and handling requirements, then verifying the revised process on representative assemblies. [1]
A soft-termination MLCC introduces a compliant layer within the termination structure to reduce strain transfer into the ceramic. The TDK guidance describes a conductive-resin layer; the Walsin ST guidance describes a flexible polymer layer. Both are intended to improve resistance to mechanically induced cracking. [2][4]
These constructions merit evaluation where unavoidable mechanical exposure remains, where a larger ceramic package is required, or where the consequence of a crack justifies additional protection. The TDK guide highlights larger EIA sizes such as 1210, 1812, and 2220 as applications where flex, thermal gradients, thickness, and crack risk deserve increased attention. [2]
| Countermeasure | Primary engineering purpose | Appropriate evaluation trigger | What it does not replace |
|---|---|---|---|
| Placement or support change | Reduce the applied mechanical loading | A clear local load path or support gap | Validation of the revised assembly |
| Controlled depanelization | Reduce strain introduced during separation | Failures or strain peaks associated with panel breakup | Control of later assembly operations |
| Soft termination | Reduce strain transferred through the termination | Residual flex exposure or constrained placement | Sound layout and process control |
| Open-mode MLCC construction | Reduce the likelihood that a typical crack creates a short | Short-circuit consequences dominate the risk assessment | Evaluation of all relevant failure modes |
| Internal series construction | Reduce direct-short risk through internal electrode architecture | Additional crack-related fault mitigation is needed | Circuit-level protection and validation |
| Alternative capacitor technology | Avoid reliance on the same ceramic construction for that function | Mechanical exposure or fault consequence remains unacceptable | Electrical and mechanical redesign review |
TDK’s open-mode construction increases separation between the external termination and active electrode area, aiming to make a common flex crack more likely to produce an open rather than a short. Its serial design places two capacitor sections in series within one body. Neither construction should be described as universally fail-safe. [2]
Walsin ST is described as an X7R, AEC-Q200-compliant soft-termination family. That qualification and construction are useful selection attributes, not proof that a particular board and assembly process are safe. [4]
Do not confuse soft termination with a termination intended for conductive-epoxy attachment. The TDK guide distinguishes its solderable conductive-resin soft termination from AgPdCu conductive-epoxy termination. They are not interchangeable assembly choices. [2]
If a mechanically vulnerable location cannot be improved sufficiently, reconsider whether the circuit function requires an MLCC there. The supplied comparison identifies film capacitors as having less ceramic-flex sensitivity and tantalum capacitors as having different failure modes. That supports a technology review, not a blanket recommendation to replace ceramics. [6]
Use the review to ask:
For every candidate, compare effective capacitance, impedance versus frequency, ESR, ESL, rated voltage, waveform capability, temperature range, dimensions, mounting requirements, and failure consequences. Those are qualification tasks, not properties to assume from the technology label. [2][4]
The same caution applies when substituting a smaller or differently terminated MLCC. Exact-part DC-bias behavior matters. A nominally equivalent X7R replacement may not provide the same effective capacitance at operating voltage. [2][4]
A useful corrective-action package contains more than a new capacitor part number. It should preserve the connection between observed damage, the identified loading mechanism, and the verified correction.
Include:
Treat a change from soft termination to standard termination as an engineering change, not a purchasing-only substitution. Likewise, preserve open-mode or internal-series construction when those features carry the design’s reliability intent. [2]
Revisit the validation when board thickness, panel configuration, connector mechanics, enclosure geometry, or fixture support changes materially. A strain audit qualifies a defined configuration and process; it is not a permanent property of the schematic.
Yes. Board deformation can crack the ceramic body without an immediate, detectable electrical failure, and a capacitor can also pass in-circuit test before a later operation such as depaneling, connector insertion, or screw fastening damages it. A passing test is not proof of ceramic integrity. [1][5][6]
Board flex transfers mechanical strain through the soldered terminations into the brittle ceramic. Sources named in the research include depanelization, connector insertion, enclosure assembly, handling, press-fit operations, screw tightening, rework, and mechanical or thermal shock. Local deformation and orientation matter, not only distance from the board edge. [1][6]
A short identifies the failed part, not the mechanism. Correlate when the failure first appeared, where failures cluster, what changes the failure rate, and what physical analysis shows, and measure the actual voltage across the capacitor terminals instead of assuming margin from the nominal rail. [1][2][4]
They reduce the strain transferred through the termination into the ceramic, using a conductive-resin or flexible polymer layer, but they do not make a mechanically poor layout or depaneling process safe. Fix the load path first and treat soft termination as added protection against residual exposure. [1][2][4]
No. Strain measurement shows how much the board deforms during a real operation, which makes the damaging step visible, but it does not directly detect a crack or convert board strain into capacitor lifetime. Use it alongside an explicit, component-relevant acceptance basis and failure analysis. [3]
AI-driven workflows such as IntelCAD.ai can help organize mechanical-risk requirements alongside schematic and PCB decisions. A useful review workflow would flag capacitors near identified separation features or load paths, retain special termination requirements in component selection, and surface the electrical tradeoffs of relocating or replacing a capacitor.
The boundary is important: design automation cannot infer the real operator handling sequence from a schematic or certify that an assembled board contains no latent cracks. Its best role is to make risks and verification tasks harder to overlook, while strain measurement, failure analysis, and controlled manufacturing establish whether the solution works.
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