Why a multiplexed SAR ADC reads the previous channel: analog multiplexer charge injection, sampling kickback, source impedance, and short acquisition time. Learn to budget settling, size the ADC driver and RC network, and test worst-case channel switching.
Your sensor voltages look correct on a meter, each channel works when sampled alone, and the board fails only when firmware starts scanning. That combination points toward a dynamic acquisition problem: the multiplexer, driver, and ADC sampling network have not forgotten the previous channel before the next conversion begins. The fix is to treat analog multiplexer selection and SAR ADC sampling as one timed analog operation, not to average more readings.
A multiplexed SAR ADC front end can produce an especially misleading failure: plausible, repeatable readings that depend on the preceding channel. A low-voltage input may read high after a high-voltage input, while the same channel reads correctly when continuously sampled. Deliberately reversing the scan order and comparing first samples with subsequent samples is a useful way to expose this behavior. [2][3]
The underlying problem is often incomplete settling rather than conventional electromagnetic coupling between PCB traces. In a simple model, some of the previous voltage remains on a capacitance when the next measurement is captured. Real boards add multiplexer switching transients, amplifier recovery, filters, and a switched-capacitor ADC input. All of these belong in the same settling budget. [1][2][3]
Start with three observations:
Save the raw conversions. Averaging can reduce random noise, but it does not reliably remove a deterministic error that repeats with every scan. If each retained reading is biased toward the previous input, averaging makes the biased result look more stable. The first-order sampling model explicitly predicts a systematic residual, not an independent noise contribution. [6]
An analog multiplexer is not an ideal selector. Changing its control state redistributes charge associated with its switches and parasitic capacitances. Some of that charge reaches the analog path, creating a transient in addition to the intended channel-to-channel voltage step. The complete signal chain must recover from the switching event; a multiplexer switching-time or bandwidth specification alone does not establish conversion accuracy. [3]
For design screening, model injected charge as a disturbance at the affected node:
$$ \Delta V_{\mathrm{inj}} \approx \frac{Q_{\mathrm{inj}}}{C_{\mathrm{node}}} $$
This is a charge-conservation estimate, not a replacement for the selected multiplexer’s specifications. A larger node capacitance can reduce the initial voltage disturbance, but that same capacitance can take longer to charge after selecting a different input. Consequently, adding capacitance may improve the visible switching spike while worsening the first conversion.
Check charge injection, on-resistance, switching behavior, and off-channel coupling in the actual device documentation. Their relevance depends on where the multiplexer sits relative to the driver and filter.
A conventional capacitive SAR input alternates between acquisition and conversion. During acquisition, a switch connects the external source to an internal sampling network. During conversion, the captured charge is used by the successive-approximation process. The source therefore drives a dynamic switched-capacitor load, not simply a high-impedance DC input. [1][5]
When the sampling switch closes, charge must move between the external circuit and the sampling capacitance. The resulting transient is commonly described as sampling kickback. A local capacitor can supply some of this fast charge, while a series resistor helps isolate the amplifier from the capacitive load. [5]
Do not assume every SAR retains the previous input voltage in exactly the same way. Internal switching and charge redistribution are device-dependent. Previous-channel voltage is a useful worst-case screening condition, but final verification must use the converter’s input model and acquisition timing. [2]
The relevant source impedance includes more than the sensor’s nominal output resistance. Include the sensor output stage, divider, cable, protection resistance, filter, multiplexer, and any amplifier output impedance that matters during the transient. A source that appears satisfactory under a high-impedance DC measurement may not supply short charging pulses adequately. [2]
This distinction explains why a board can pass with a laboratory source but fail with the intended sensor. A low-impedance test source can conceal a problem caused by the actual sensor, divider, or cable. The channel-switching test must preserve representative source impedance. [3]
The ADC only captures the voltage reached by its sampling network at the end of acquisition. Any residual settling error at that instant becomes part of the digital result. [1][6]
The sample period is not necessarily the acquisition period. The research gives a useful example: a rate of 100 ksample/s means a 10 µs sample period, but the selected timing mode might provide only 1 µs of acquisition. Using the full 10 µs in a settling calculation would be optimistic by a factor of ten. [2]
Reducing throughput helps only if it extends an interval that actually matters: external signal-chain settling, internal acquisition, or both. Waiting while the sampling switch is open can let an external amplifier recover without charging the internal sampling capacitor. Verify the timing rather than assuming that a slower trigger automatically fixes everything. [2]
Mark these events explicitly:
The intervals can overlap, but only where the selected hardware permits it. The research recommends documenting channel selection, switching, acquisition, conversion start, and data association together because the entire analog path, not just the multiplexer, must settle. [3]
For an MCU ADC, inspect the channel-specific sample-time configuration and ADC clock settings. Confirm that a library call or later firmware change has not shortened the acquisition window. Record the converter part number and revision, resolution, full-scale span, actual acquisition duration, and worst preceding-channel voltage. [2]
Separate two budgets:
These budgets interact, but they are not interchangeable. An already-settled ADC pin is an initial condition for acquisition, not proof that the internal capacitor reaches the required accuracy.
For an ideal N-bit converter with full-scale input span V_FS:
$$ V_{\mathrm{LSB}}=\frac{V_{\mathrm{FS}}}{2^N} $$
A half-LSB settling allowance is:
$$ V_{\mathrm{allowed}}=\frac{V_{\mathrm{FS}}}{2^{N+1}} $$
That allowance covers settling only. It does not include reference error, offset, gain error, integral nonlinearity, or noise. A system error budget may allocate substantially less than half an LSB to settling. [2]
For a first-order network with time constant τ = RC, the residual following a voltage step ΔV is:
$$ V_{\mathrm{error}}=|\Delta V|e^{-t/\tau} $$
Therefore:
$$ t\geq \tau\ln\left(\frac{|\Delta V|}{V_{\mathrm{allowed}}}\right) $$
For a full-scale step and half-LSB allowance, this becomes t ≥ (N + 1) ln(2) × τ. The following screening values come directly from the research. [2][6]
| Resolution | Required settling time | Time with RC = 100 ns |
|---|---|---|
| 10 bits | 7.625 τ | 762.5 ns |
| 12 bits | 9.011 τ | 901.1 ns |
| 14 bits | 10.397 τ | 1.040 µs |
| 16 bits | 11.784 τ | 1.178 µs |
The practical lesson is that a waveform that looks settled on an ordinary oscilloscope display may still be far outside the converter’s error budget.
The research considers an illustrative total resistance of 5 kΩ driving 20 pF, giving τ = 100 ns. For a 12-bit converter and a full-scale step, the ideal half-LSB settling time is approximately 901 ns. [2]
With only 500 ns available, the residual is approximately 0.674% of full scale, or 27.6 LSB. At 1 µs, the same model predicts approximately 0.186 LSB. These are calculated first-order results, not guaranteed performance for a particular ADC. [2]
A second example uses a 50 kΩ Thevenin source resistance and 5 pF sampling capacitance. The time constant is 250 ns, and 12-bit settling requires approximately 2.25 µs. A 1 µs acquisition window is therefore inadequate under that model. [6]
Both examples show why checking only DC input voltage or input leakage can miss the dominant error.
Real circuits include amplifier bandwidth, slew-rate limits, voltage-dependent switch resistance, and internal charge redistribution. A first-order calculation is a screening tool. It is not a proof for a multipole or nonlinear signal chain. [2]
Use it to establish whether the design is plausibly fast enough. Then assess the amplifier’s large-signal transition, precision settling tail, capacitive loading, and recovery from each sampling event. If several effects consume the settling budget, do not independently allow each one the entire half-LSB error.
A shared buffer after the multiplexer lowers the impedance presented to the ADC, but it must also follow the full channel-to-channel voltage step. Per-channel buffers can isolate high-impedance sensors before multiplexing, although the shared path and ADC sampling network still require settling analysis.
For either arrangement, evaluate these driver properties together:
Unity-gain bandwidth alone is not a settling guarantee. The research specifically identifies output recovery, stability with the proposed capacitance, supply range, and combined driver/filter response as review items. [2]
For intuition, a hypothetical single-pole closed-loop response has τ = 1/(2πf_CL). Substituting this into the settling inequality gives:
$$ f_{\mathrm{CL}}\geq\frac{\ln(|\Delta V|/V_{\mathrm{allowed}})}{2\pi t_{\mathrm{settle}}} $$
This is a derived screening relationship, not an op-amp selection rule. It ignores slew limiting, additional poles, output-current limits, and capacitive-load effects. Select the driver using applicable settling and load data, then validate the complete network.
A small series resistor between the amplifier output and the ADC-pin capacitor can improve capacitive-load behavior and isolate sampling kickback. However, it also adds resistance to the charging path. Increasing it until ringing disappears can create a quieter-looking but slower front end. [2][5]
Review the exact feedback topology. A resistor placed outside the feedback loop does not behave like one enclosed by feedback around the capacitive node. Use the amplifier manufacturer’s supported configuration and simulation model where available, then verify on hardware.
Probe the amplifier output and ADC pin separately. Ringing at the output suggests a different corrective action from a clean amplifier output followed by a slowly settling ADC-pin voltage. Use low-loading probes and short connections so the measurement does not substantially change the network being tested.
The usual local network is a series isolation resistor followed by a capacitor at the ADC input. The capacitor supplies fast sampling charge; the resistor isolates the driver; together they also filter the signal. Those functions impose competing constraints. [5]
A useful idealized charge-sharing model assumes an external capacitor C_EXT already at the new channel voltage and a sampling capacitor C_S at a different voltage. Immediately after connection:
$$ |\Delta V_{\mathrm{pin}}|\approx\frac{C_S}{C_{\mathrm{EXT}}+C_S}|\Delta V| $$
The source must then restore the lost charge. If the external capacitor is instead on the shared multiplexer output and still holds the preceding channel voltage, it must first settle toward the new channel; the favorable initial condition above does not apply. [6]
One supplied driver guide presents a reservoir-sizing heuristic of C_EXT ≥ 20 × C_S. Treat that only as a starting point for reducing kickback, not as proof of sub-LSB accuracy. [5]
Using the charge-sharing model, a capacitor exactly 20 times larger produces an immediate disturbance equal to 1/21 of the initial voltage difference. That derived result is plainly not a precision-settling guarantee. To achieve half-LSB accuracy through charge sharing alone, with no subsequent recharge, the ideal full-scale-step condition is:
$$ C_{\mathrm{EXT}}\geq C_S(2^{N+1}-1) $$
That much larger requirement appears in the research and illustrates why active recovery during acquisition is essential. [6]
The supplied driver example uses 20 Ω and 1.5 nF, producing an RC time constant of 30 ns. [5] Applying the 16-bit half-LSB factor gives approximately 354 ns for an ideal full-scale step; this is a calculation from that example, not a measured settling specification. [2][5]
The real circuit must additionally accommodate amplifier output impedance, internal ADC switching resistance, component tolerances, and any upstream poles. A network that passes the resistor-capacitor calculation can still fail because the amplifier rings or recovers too slowly. [2]
Use this sequence:
The local RC network also attenuates high-frequency content, but one pole is not automatically adequate anti-alias protection. The research notes that a first-order RC has limited stop-band attenuation and that additional filtering may be necessary. [5]
For a scanned system, distinguish aggregate ADC throughput from each channel’s sampling rate. Evaluate aliasing against the actual sample sequence of each sensor. Meanwhile, the shared output network must settle between different channel voltages.
This creates an architectural tension: a low shared filter corner may suppress noise but retain the preceding channel’s voltage too long. Per-channel filtering before the multiplexer can address sensor bandwidth without forcing the entire filtering capacitance to traverse every channel step, but the remaining shared network still needs acquisition analysis.
| Remedy | Best fit | Main limitation | What must be verified |
|---|---|---|---|
| Extend acquisition | Internal sampling network cannot settle through source impedance | Reduces available conversion throughput | The programmed change actually lengthens acquisition |
| Add delay after channel selection | Multiplexer output, driver, or shared filter needs recovery | May not extend internal acquisition | ADC switch state during the delay |
| Discard dummy conversions | Repeated acquisition lets the path converge | Consumes throughput; one discarded result may be insufficient | Every retained sample meets the budget |
| Reduce scan rate | More recovery time is acceptable | Some modes preserve the same short acquisition window | Which analog interval actually becomes longer |
| Improve buffering or RC network | Source impedance, kickback, or driver stability is limiting | Adds power, complexity, and possible noise | Complete driver/filter settling |
| Use simultaneous sampling | Interchannel timing alignment or serial-settling overhead is unacceptable | Different cost, power, and interface tradeoffs | Genuine simultaneous acquisition and per-input drive requirements |
Discarding the first conversion is a legitimate engineering choice when verified, not a universal cure. The research emphasizes that the remaining delay must be sufficient under all required conditions and that discarded samples must be correctly associated with their channels. [3]
Also check the ADC’s internal behavior: repeated conversions do not necessarily accumulate settling exactly as an always-connected RC would. Each acquisition can introduce a new disturbance.
Reordering channels can reduce typical voltage steps, but it is fragile if sensor values change or firmware later changes the sequence. Save the validated scan order with the test results. [3]
Simultaneous-sampling hardware becomes attractive when serial acquisition cannot satisfy both settling and timing requirements. However, “multichannel” does not itself establish simultaneous acquisition. Confirm the sampling architecture, and remember that eliminating a shared channel-switching step does not eliminate each input’s source-impedance and kickback requirements.
A useful acceptance test deliberately creates the condition that normal operation may encounter only occasionally.
Drive two channels with stable low and high voltages within their permitted input range. Use the actual sensor-equivalent impedance, including relevant divider and filter networks. First sample each channel repeatedly without switching to establish its steady-state baseline. [2][3]
Record baseline mean and spread separately from switching error. If absolute accuracy matters, compare against suitable reference equipment rather than treating the ADC’s repeated-channel value as an absolute truth.
Alternate low-to-high and high-to-low transitions. Then hold the newly selected channel for several conversions and retain every result. Reverse the order and repeat with different predecessor channels. These are recommended ways to expose history-dependent settling. [2][3]
For each conversion, log:
Trigger the oscilloscope from channel selection or conversion control. Observe the shared analog node, driver output, and relevant timing signals where practical. Compare the waveform at the actual sampling instant, not simply its eventual settled value.
Run controlled experiments:
A predecessor-dependent error that decreases with acquisition time strongly supports a settling explanation. A persistent error after generous settling requires broader investigation: channel/data misassociation, static transfer errors, leakage, reference disturbance, or coupling may coexist.
Define acceptance around the first retained sample. Its switching-induced deviation must fit the allocated budget in both directions and across the specified conditions. Also verify subsequent samples and sustained scanning; a transient test alone does not establish all aspects of converter accuracy.
These layout checks support the dynamic model; they do not replace it. A correct schematic can lose its settling margin through parasitic impedance, coupling, or an unfavorable driver implementation. [2]
Usually because the front end has not finished settling. Some of the previous channel's voltage remains on a capacitance when the next sample is captured, and multiplexer switching transients, amplifier recovery, filters, and the switched-capacitor SAR ADC input all add to that residual. [1][2][3]
Often it is not. The error is frequently incomplete settling rather than conventional electromagnetic coupling between PCB traces. Reversing the scan order and comparing the first sample with later samples on the same channel helps expose this history-dependent behavior. [2][3]
For a full-scale step and a half-LSB settling allowance in a first-order model, the required time is (N + 1) ln(2) time constants: about 9.01 τ at 12 bits and 11.78 τ at 16 bits. Measure that against the actual acquisition window, not the full sample period. [2][6]
No. Averaging reduces random noise, but a settling residual is a deterministic error that repeats on every scan, so averaging only makes the biased result look more stable. [6]
It can be a legitimate fix when verified, but it is not a universal cure. One discarded result may be insufficient, every retained sample must meet the error budget, and discarded samples must stay correctly associated with their channels. [3]
A local charge-reservoir capacitor reduces sampling kickback, but a large capacitor on the shared multiplexer output can hold the preceding channel's voltage longer. The C_EXT ≥ 20 × C_S guideline is only a starting point, not proof of sub-LSB accuracy. [5][6]
AI-driven workflows such as IntelCAD.ai can help turn an acquisition requirement into a schematic draft and a structured review: channel impedances, worst-case voltage steps, driver loading, RC values, and required timing should all be explicit inputs. They can also help maintain consistency between the schematic, firmware timing assumptions, and bench-test checklist.
The useful role is to expose missing constraints early, not to substitute a generic component recommendation for device-specific evidence. Final confidence still comes from the selected ADC and amplifier documentation, appropriate simulation, and a worst-case channel-switching test on the actual board.
Design your next board by describing it.
IntelCAD.ai turns plain-language requirements into schematics and PCBs.
Start Your Design