Oct 29, 2026

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Decoupling Capacitor Guide: How to Choose Values and Place Them on a PCB

Learn what a decoupling capacitor does, how to pick values and package sizes, and where to place it on a PCB, plus common mistakes and how AI helps.

Decoupling capacitors placed around an IC on a PCB for local power supply noise filtering

Short answer: A decoupling capacitor is a small capacitor placed between a chip’s power pin and ground to supply fast bursts of current locally and keep the supply voltage steady. Pick a mix of values (often a 100 nF ceramic per power pin plus a 1 to 10 µF bulk capacitor per rail), use X7R or X5R ceramics in small packages, and place each capacitor as close to its power pin as possible with short, wide connections and vias straight down to a solid ground plane. Check the capacitance at your real DC bias voltage, not just the label value. AI tools help by choosing parts that are in stock, flagging capacitors placed too far from their pins, and checking the decoupling network against the chip’s datasheet.

What is a decoupling capacitor?

Every digital chip draws current in short, sharp bursts each time its transistors switch. The power supply and the traces feeding the chip have inductance, so they can’t respond instantly. Without help, the voltage at the chip’s power pin dips and rings with every burst. That noise can cause logic errors, jitter on clocks, poor ADC readings and extra EMI.

A decoupling capacitor sits right next to the power pin and acts as a tiny local energy store. When the chip suddenly needs current, the capacitor supplies it, and the supply recharges the capacitor more slowly. The result is a much steadier voltage at the pin and less noise spreading to the rest of the board.

Decoupling capacitor vs bypass capacitor

Engineers often use the two terms for the same part. When people separate them:

Bypass capacitor usually means a capacitor that shunts high-frequency noise on a supply to ground, “bypassing” it around the chip.
Decoupling capacitor usually means a capacitor that isolates (decouples) one circuit’s switching noise from the rest of the power network.

In practice, the same 100 nF ceramic next to an MCU power pin does both jobs, so the design rules below apply to either name.

How to choose a decoupling capacitor value

No single value works across all frequencies. Every real capacitor has some parasitic inductance (ESL) and resistance (ESR), so it only acts like a capacitor up to its self-resonant frequency. Above that, it behaves like an inductor. That’s why designs use several values in parallel, each covering a different frequency band:

Three ceramic decoupling capacitors of different sizes in parallel near a chip on a PCB

Bulk capacitors (1 to 100 µF): one or a few per power rail, near where power enters the board or a group of chips. They handle slower, larger current changes.
Local decoupling (100 nF, sometimes 1 µF): one per power pin or pin pair. This is the workhorse for most MCUs, logic and interface chips.
High-frequency capacitors (1 to 10 nF): for fast FPGAs, processors and RF parts, where the datasheet calls for them.

Start with the datasheet. Chip vendors often specify exact values, counts and placement for each power pin. Follow those first, then add your own margin.

Decoupling capacitor selection: package, dielectric and DC bias

The decoupling capacitor value printed on the reel is only the starting point. Real performance depends on:

Dielectric: use X7R or X5R ceramics for decoupling. Y5V and Z5U lose much of their capacitance with temperature and voltage. C0G (NP0) is very stable but only practical in small values.
DC bias derating: a ceramic’s capacitance drops as the voltage across it rises. A 10 µF 6.3 V capacitor in a small package may only give a fraction of its rating at 5 V. Check the manufacturer’s DC bias curve and choose a higher voltage rating or a larger package if needed.
Package size: smaller packages such as 0402 have lower ESL and fit closer to pins, which helps at high frequency. Larger packages hold more capacitance at a given voltage.
Availability and second sources: capacitors look like commodities, but specific values in small packages and high voltage ratings do go on allocation. Choose parts with several sources and stable lifecycles.

Decoupling capacitor placement rules

Placement matters as much as value. A perfectly chosen capacitor placed 20 mm away from its pin does little at high frequency, because the trace adds inductance. Good decoupling capacitor placement follows a few rules:

Close-up of an SMD decoupling capacitor next to an IC power pin with short vias to the ground plane

Put the smallest-value capacitor closest to the pin. It handles the fastest current changes and is the most sensitive to extra inductance.
Keep the loop small. The current path runs from the capacitor to the power pin, through the chip, out the ground pin and back to the capacitor. Minimize the area of that loop.
Use short, wide connections. Avoid long thin traces between the capacitor pads and the pins.
Drop vias straight to the planes. Place ground and power vias right at the capacitor pads, or use via-in-pad where your fabricator supports it.
Use a solid ground plane close to the surface. A stackup with the ground plane directly under the component layer keeps the via inductance low.
Place capacitors on the same side as the chip when possible. Under a BGA, capacitors on the bottom side directly beneath the power balls are a common, effective option.
Connect the supply through the capacitor first. Route power so it reaches the capacitor pad and then the chip pin, not the other way around.

Decoupling capacitor PCB layout: common mistakes

Placing all decoupling capacitors in a neat row far from the chip because it looks tidy.
Sharing one via between several capacitors and pins, which adds inductance and couples noise.
Using thin, long traces to reach a distant ground via.
Ignoring DC bias derating, so a bulk capacitor delivers far less capacitance than the schematic says.
Copying the same 100 nF value everywhere without checking the chip’s datasheet or frequency needs.
Routing a split or slotted plane under the chip, which breaks the return path for the decoupling loop.

How many decoupling capacitors do you need?

A practical starting point for most boards:

One 100 nF ceramic per power pin or closely spaced pin pair.
One 1 to 10 µF ceramic per chip or per power rail near the chip.
One bulk capacitor (10 to 100 µF) per rail near the regulator or power entry.

For high-speed processors and FPGAs, follow the vendor’s power distribution network (PDN) guidelines, which often target a specific impedance across a frequency range and specify capacitor counts per rail.

Where AI helps with decoupling capacitors

Decoupling sits right where component selection and PCB layout meet, which makes it a good fit for AI assistance:

Reading datasheets to pull out each chip’s recommended decoupling values, counts and placement notes.
Choosing real parts: suggesting capacitors with the right dielectric, voltage rating and package, checking DC bias derating, stock and second sources.
Checking placement: flagging capacitors placed too far from their power pins, shared vias and long ground connections.
Cross-checking the stackup: confirming that the ground plane sits close to the component layer and that no split runs under the chip.

This is what IntelCAD is building: AI for PCB design and electronics component selection that catches decoupling problems in the schematic and layout, before they show up as noise on the bench.

FAQ

What does a decoupling capacitor do?

A decoupling capacitor supplies fast bursts of current to a chip from right next to its power pin, so the supply voltage stays steady and switching noise doesn’t spread across the board.

What value decoupling capacitor should I use?

A common starting point is a 100 nF ceramic capacitor per power pin plus a 1 to 10 µF capacitor per chip or rail. Always check the chip’s datasheet first, since many vendors specify exact values.

Is a bypass capacitor the same as a decoupling capacitor?

Mostly, yes. The terms are often used interchangeably. A bypass capacitor shunts noise to ground, while a decoupling capacitor isolates one circuit’s noise from the power network, and the same part usually does both.

How close should a decoupling capacitor be to the IC?

As close as possible to the power pin, ideally within a few millimeters, with vias placed right at the capacitor pads so the current loop stays small.

How does AI help with decoupling capacitor design?

AI can read datasheets for recommended values, pick in-stock capacitors with the right dielectric and voltage rating, account for DC bias derating, and flag poorly placed capacitors in the layout.

Next step

Want decoupling, part choice and layout checked while you design? Talk to the IntelCAD team about AI-assisted PCB design and component selection for your next board.

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